<XML><RECORDS><RECORD><REFERENCE_TYPE>3</REFERENCE_TYPE><REFNUM>6716</REFNUM><AUTHORS><AUTHOR>Susanto,K.W.</AUTHOR></AUTHORS><YEAR>2002</YEAR><TITLE>An Integrated Formal Approach for System on Chip</TITLE><PLACE_PUBLISHED>The Proceeding of the International Workshop on IP Based Design 2002</PLACE_PUBLISHED><PUBLISHER>N/A</PUBLISHER><PAGES>119-123</PAGES><LABEL>Susanto:2002:6716</LABEL><KEYWORDS><KEYWORD>Formal Verification</KEYWORD></KEYWORDS<ABSTRACT>System on chip technology will reshape common design practice. One design approach is to use intellectual property blocks to build systems in a plug and play environment called an integration platform. Sooner or later, Formal Verification will also need to address this new challenge. We propose a verification platform that is similar to this integration platform. Every component in the integration platform has a corresponding formal model in the verification platform. In the verification platform, all the formal models are connected using a kind of glue logic. The verification platform takes a hybrid form that incorporates simulation, model checking, and theorem proving capabilities. It is assembled from a mixture of existing formal reasoning tools. </ABSTRACT></RECORD></RECORDS></XML>