<XML><RECORDS><RECORD><REFERENCE_TYPE>3</REFERENCE_TYPE><REFNUM>7082</REFNUM><AUTHORS><AUTHOR>Susanto,K.W.</AUTHOR><AUTHOR>Melham,T.F.</AUTHOR></AUTHORS><YEAR>2003</YEAR><TITLE>AMBA-ARM7 Formal Verification Platform</TITLE><PLACE_PUBLISHED>To appear at the 5th International Conference on Formal Engineering Methods 2003. </PLACE_PUBLISHED><PUBLISHER>Springer Verlag</PUBLISHER><PAGES>20</PAGES><LABEL>Susanto:2003:7082</LABEL><KEYWORDS><KEYWORD>formal verification</KEYWORD></KEYWORDS<ABSTRACT>The pressure to create a working System on Chip design as early as possible leads designers to consider using a platform based design method. In this approach, designing an application is a matter of selecting from a set of standard components with compatible specifications. Subsequently, a formal verification platform can be constructed. The formal verification platform provides an environment to analysed the combined properties of the design. In this paper, we present a methodology to do formal System on Chip analysis by developing generic formal components that can be integrated in a formal verification platform. First, we develop reusable formal properties of standard components. Second, we define a generic formal platform in which components of System on Chip design can be integrated. The platform contains basic components such as a standard bus protocol and a processor. Third, we combine the properties of standard components and obtain a set of refined properties of the system. We use these properties to develop the required specifications of the remaining components. </ABSTRACT></RECORD></RECORDS></XML>