<XML><RECORDS><RECORD><REFERENCE_TYPE>0</REFERENCE_TYPE><REFNUM>8138</REFNUM><AUTHORS><AUTHOR>Miller,A.</AUTHOR><AUTHOR>Donaldson,A.F.</AUTHOR><AUTHOR>Calder,M.</AUTHOR></AUTHORS><YEAR>2006</YEAR><TITLE>Symmetry in temporal logic model checking</TITLE><PLACE_PUBLISHED>ACM Computing Surveys, volume 38, issue 3</PLACE_PUBLISHED><PUBLISHER>ACM</PUBLISHER><ISBN>0360-0300</ISBN><LABEL>Miller:2006:8138</LABEL><KEYWORDS><KEYWORD>Model checking</KEYWORD></KEYWORDS<ABSTRACT>Temporal Logic model checking involves checking the state-space of a model of a system to determine whether errors can occur inthe system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.</ABSTRACT></RECORD></RECORDS></XML>