<XML><RECORDS><RECORD><REFERENCE_TYPE>3</REFERENCE_TYPE><REFNUM>9262</REFNUM><AUTHORS><AUTHOR>Chalamalasetti,S.</AUTHOR><AUTHOR>Purohit,S.</AUTHOR><AUTHOR>Margala,M.</AUTHOR><AUTHOR>Vanderbauwhede,W.</AUTHOR></AUTHORS><YEAR>2009</YEAR><TITLE>MORA – An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor</TITLE><PLACE_PUBLISHED>2009 NASA/ESA Conference on Adaptive Hardware and Systems (AHS09)</PLACE_PUBLISHED><PUBLISHER>N/A</PUBLISHER><LABEL>Chalamalasetti:2009:9262</LABEL><ABSTRACT>This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co- design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using cycle accurate simulator are presented.</ABSTRACT></RECORD></RECORDS></XML>