<XML><RECORDS><RECORD><REFERENCE_TYPE>3</REFERENCE_TYPE><REFNUM>9267</REFNUM><AUTHORS><AUTHOR>Moadeli,M.</AUTHOR><AUTHOR>Maji,P.P.</AUTHOR><AUTHOR>Vanderbauwhede,W.</AUTHOR></AUTHORS><YEAR>2009</YEAR><TITLE>Design and implementation of the Quarc Network on-Chip</TITLE><PLACE_PUBLISHED>IEEE International Symposium on Parallel & Distributed Processing, 2009. (IPDPS09-RAW).</PLACE_PUBLISHED><PUBLISHER>IEEE</PUBLISHER><PAGES>1 - 9</PAGES><ISBN>1530-2075</ISBN><LABEL>Moadeli:2009:9267</LABEL><KEYWORDS><KEYWORD>network-on-chip packet switching</KEYWORD></KEYWORDS<ABSTRACT>Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip. However, to successfully replace its predecessor, the NoC has to be able to efficiently exchange all types of traffic including collective communications. The latter is especially important for e.g. cache updates in multicore systems. The Quarc NoC architecture has been introduced as a Networks-on-Chip which is highly efficient in exchanging all types of traffic including broadcast and multicast. In this paper we present the hardware implementation of the switch architecture and the network adapter (transceiver) of the Quarc NoC. Moreover, the paper presents an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs implemented in Verilog targeting the Xilinx Virtex FPGA family. We demonstrate a dramatic improvement in performance over the Spidergon especially for broadcast traffic, at no additional hardware cost.</ABSTRACT></RECORD></RECORDS></XML>