<XML><RECORDS><RECORD><REFERENCE_TYPE>3</REFERENCE_TYPE><REFNUM>9272</REFNUM><AUTHORS><AUTHOR>Moadeli,M.</AUTHOR><AUTHOR>Maji,P.P.</AUTHOR><AUTHOR>Vanderbauwhede,W.</AUTHOR></AUTHORS><YEAR>2009</YEAR><TITLE>Quarc: a High-Efficiency Network on-Chip Architecture</TITLE><PLACE_PUBLISHED>The IEEE 23rd International Conference on Advanced Information Networking and Applications (AINA-09)</PLACE_PUBLISHED><PUBLISHER>IEEE</PUBLISHER><PAGES>99-105</PAGES><LABEL>Moadeli:2009:9272</LABEL><KEYWORDS><KEYWORD>Networks-on-Chip</KEYWORD></KEYWORDS<ABSTRACT>The novel Quarc NoC architecture, inspired by the Spidergon scheme [5] is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC. This paper provides an ASIC implementation of both architectures using UMC’s 0.13µm CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs.</ABSTRACT></RECORD></RECORDS></XML>