UNIVERSITY of GLASGOW

Computing at Glasgow University
 
Paper ID: 9271

High-level Programming of Dynamically Reconfigurable NoC-based Heterogeneous Multicore SoCs
Vanderbauwhede,W.

Publication Type: Chapter in Book
Appeared in: Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
Page Numbers :
Publisher: Idea Group Publishing
Year: 2010
ISBN/ISSN: 1615208070
Abstract:

With the increase in SoC complexity sand CMOS technology capabilities, the SoC design community has recently observed a convergence of a number of critical trends, all of them aimed at addressing the design gap: the advent of heterogeneous multi-core SoCs and Networks-on-Chip and the recognition of the need for design reuse through IP cores, for dynamic reconfigurability and for high abstraction-level design. In this chapter, we present a solution for High-level Programming of Dynamically Reconfigurable NoC-based Heterogeneous Multicore SoCs. Our solution, the Gannet framework, allows IP core-based Heterogeneous Multicore SoCs to be programmed using a high-level language whilst preserving the full potential for parallelism and dynamic reconfigurability inherent in such a system. The required hardware infrastructure is small and low-latency, thus adding full dynamic reconfiguration capabilities with a small overhead both in area and performance.

Keywords: networks-on-chip, dynamic reconfiguration, CGRA


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