2nd Workshop on Programming and Design of Heterogeneous and Reconfigurable Systems

Topics

There is a growing interest in computing architectures that provide an alternative to the conventional von Neumann model. Computing systems increasingly incorporate heterogeneous elements, either at processor level , e.g. the Cell processor, or at system level, e.g. Graphical Processing Units (GPUs). Furthermore, with the drive towards low-power architectures, both fine-grained reconfigurable fabrics such as Field-Programmable Gate Arrays (FPGAs) and coarse-grained reconfigurable architectures (CGRAs) are gaining in popularity.

All these novel architectures have distinct programming models, especially distinct concurrency and memory models, which are not supported well by existing programming languages. High-level programming of heterogeneous and reconfigurable systems is therefore a key challenge in programming language research. Equally important, novel architectures must be designed for high-level programmability.

Objectives

This informal workshop will bring together UK researchers from the heterogeneous and reconfigurable hardware and programming languages communities. The main aim of the workshop is to increase mutual understanding between the communities and to encourage interdisciplinary communication.

Format

The workshop will have a keynote talk by Satnam Singh (Microsoft Research) and as many contributed talks as you contribute. We expect plenty of challenging ideas, and plenty of time for discussion.

Slots will be 30 minutes and we have room for about 15 talks. If we're overwhelmed, a selection will be made depending on the balance of topics received. As this is a workshop, no formal proceedings will be published.

Venue

The workshop will be held in the Department of Computing Science, in the conference room at the top level of the Sir Alwyn Williams Building.

Key dates:

• submission of slides by 23rd July 2010,
• workshop 4th-5th August 2010.