Curriculum Vitae

Education & Training

Degree in Electrotechnical Engineering (Specialisation Physics) with Great Distinction University of Ghent (Belgium) - October 1986 till July 1991
Ph.D. in Applied Sciences (Specialisation Opto-Electronics) with Greatest Distinction University of Ghent (Belgium) - September 1991 till December 1996

Employment

Current (from April 2004): Lecturer
Department of Computing Science, University of Glasgow, Glasgow (UK).
From October 2004 till September 2009, EPSRC Advanced Research Fellow, researching Service-base System-on-Chip architectures.
October 2001 - March 2004: Research Fellow
Broadband and Optical Networks Group, Institute for Communications and Signal Processing, EEE Department, University of Strathclyde, Glasgow (UK).
- Responsible for the system-level design and performance modeling of an asynchronous optical packet switch in the framework of the EPSRC project OPSnet.
  - Major tasks:
    - System-level design and modeling of the optical switch fabric and the electronic control system. More...
      
      The OPSnet switch adopts a novel optical buffer architecture which has very low packet latency and loss. The optical design involves trade-offs between cost, performance and complexity and requires the evaluation of different physical layer solutions.
      The control system is an event-driven asynchronous hardware design, implemented in Verilog. The use of an object-oriented code generator allows for easy configurability and optical-electronic co-design and co-simulation for behavioural modeling. For the final demonstrator, the design will be realized using a Xilinx FPGA.
      The Verilog description of the switch has been ported to a high-level C++ model. This model allows simulation of the impact of traffic distributions and traffic aggregation, buffer control policies, such as ordering and DiffServ prioritization, evaluation of the performance of different buffer designs and the resulting buffer depth requirements.
    - Definition and follow-up of undergraduate student and research student projects. More...
      
      The students projects relate to specific subtasks of the optical packet switch design. Examples are physical layer modeling of a recirculating buffer module and Verilog design and FPGA implementation of a scrambling technique to improve the bit error rate of the optical signal.
    - Responsible for the system administration for the Broadband and Optical Networks (BON) research group network. More...
      
      The BON group network consists of Linux, Solaris and Windows desktop machines and Linux servers. The key tasks are ensuring cross-platform accessibility of simulation resources and network folders, as well as ensuring smooth interaction with the DHCP, NIS and NFS servers of the Department.
  - Achievements:
    - Publications and presentations of research results. More...
      
      The research work has been presented on several international conferences. The software tools developed in the frame of the project have been made available to the design community via the internet
      (see list of publications for details).
    - Deployment of the Broadband and Optical Networks research group network. More...
      
      The BON network did not exist at the start of the assignment. Building the network included setting up Linux servers and dual-boot desktops, managing accounts, installing software and configuring services (CUPS/SMB print server, NFS/SMB file server, simulation server, NIS slave server). Other tasks include designing tools and strategies for simulation management , and designing and implementing the interactive BON group web site.
August 1998-October 2001: Senior Technology R&D Engineer
Technology R&D Department, Alcatel Microelectronics - Oudenaarde (Belgium), an integrated circuits (IC) design and manufacturing company
- The Technology R&D Engineer is responsible for qualifying technologies and supplying the Design Engineers with design model kits.
  - Major tasks:
    - Qualifying IC manufacturing processes of external suppliers. More...
      
      The starting point in the qualification process is the assessment of process performance by simulating benchmark circuits using SPICE parameters provided by the external supplier. The Technology R&D Engineer is responsible for the implementation and interpretation of the benchmark simulations. He also designs and evaluates the test circuits used for characterisation of the supplier's processed material. He closely cooperates with R&D and Process Engineers of the external supplier as well as with in-house Test Engineers.
    - IC Performance failure analysis. More...
      
      Performance failure cases during final product testing are investigated by the Design Optimization Team, a multi-disciplinary team of Test Engineers, Yield Engineers, Design Engineers and Technology R&D Engineers. The task of the Technology R&D Engineer is to simulate the observed failure behaviour and propose a solution via redesign or tuning of the manufacturing process. This requires a thorough understanding of the circuit architecture and of the influence of the device model parameters on the circuit behaviour.
    - Developing and maintaining design model kits. More...
      
      The Technology R&D Engineer is responsible for developing and maintaining the SPICE models for all process-specific device types. The quality of the SPICE model design kit is one of the key factors in state-of-the-art mixed mode circuit design.
  - Achievements:
    - Digital design and full Verilog and SPICE simulation of an ASIC for the characterisation of CMOS digital libraries. More...
      
      The generic digital qualification ASIC concept allows for complete characterisation of logic gates and interconnect metalisation, full test coverage, easy and fast automatic testing and complete SPICE characterisation of a 6 million transistor chip. The design can easily be ported to new technology generations, and has been implemented in 0.25 μm and 0.18 μm gate length processes.
    - Yield problem solution for a high-volume GSM baseband ASIC. More...
      
      The root cause for failure was identified via analysis of the layout database and via analogue SPICE simulation of the extracted netlist. The proposed solution was cost-effective and has been implemented successfully.
    - Implementation of a Poisson field solver in generic SPICE. More...
      
      The Poisson field solver uses a standard SPICE simulator to calculate the capacitance of arbitrary 2D interconnect structures. The user interface consists of a Microsoft Excel worksheet. An Excel Visual Basic script constructs the finite difference grid and converts it into a SPICE netlist. The tool was shown to be as fast and as accurate as the industry standard (Avant! RAPHAEL) and was very valuable in evaluating multi-layer interconnect structures used in deep submicron CMOS technologies.
August 1996 - August 1998: Mixed-Mode Design Engineer
Design Department, Alcatel Microelectronics - Brussels (Belgium), an integrated circuits design and manufacturing company
- The Design Engineer is responsible for all phases of the IC design process.
  - Major tasks:
    - Designing mixed-mode CMOS ASICs for telecommunication applications. More...
      
      Starting from the customer's specifications, the Design Engineer performs a feasibility study during which the architecture of the ASIC and the building blocks are defined and the technology is selected. Each member of the design team is responsible for the design, simulation and layout of a set of building blocks.
    - Verifying prototypes and preparing the product release. More...
      
      The Design Engineer is responsible for verifying the prototypes on an experimental test bench. Using these test bench results, he evaluates the prototype performance and provides input for debugging the automatic test routines. He is also in charge of organizing reliability tests and assisting the customer with on-site evaluation.
  - Achievements:
    - Design of a mixed-mode front-end ASIC for an SDSL modem. More...
      
      The ASIC, which was implemented using a 0.5 μm CMOS process, contains a analogue adaptive echo-canceler for which a patent has been filed.
    - Design of a mixed-mode front-end ASIC for a cable modem. More...
      
      The ASIC, which was implemented using a 0.35 μm CMOS process, contains a new type of capacitor for which a patent has been obtained.
September 1991 - December 1996: PhD in Applied Sciences (Specialisation Opto-Electronics)
Department of Information Technology, Faculty of Applied Sciences, University of Ghent (Belgium)
- - Major task:
    - Design, simulation, fabrication and characterisation of a guided-wave tunable demultiplexer for use in Wavelength Division Multiplexing optical communication networks. More...
      
      The component was fabricated in InP-based III-V semiconductors using MOVPE. The Ph.D. work consisted of the design and modelling of the component and the development of the complete process flow.
  - Achievements:
    - Development of simulation software based on the Mode Expansion and Propagation Algorithm. More...
      
      The program simulates filter spectra, coupling efficiency and coupling length based on the initial 2D waveguide mode profile, and allows to study the effects of process non-uniformities. It was an essential tool in the design of the component and the analysis of the measurement results.
    - Realisation of a narrow-bandwidth polarization-independent tunable filter with integrated detector. More...
      
      The filter-detector integration was the first to be reported in literature, and the bandwidth was the best reported value for this filter type. A multiple quantum well structure with a new material combination was used.

List of publications and patents