Call for Book Chapters
High-Performance Computing using FPGAs
Proposals Submission Deadline: December 15, 2011
Full Chapters Due: March 28, 2012
Publisher: Springer
Background
In recent years, several research groups have built FPGA-based parallel machines e.g. the Maxwell system at the University of Edinburgh, or the CONFETTI system at EPFL; there are also a number of companies that offer FPGA-based HPC solutions, e.g. The DINI group, PicoComputing. In last year’s SuperComputing (SC10) conference there was a lot of interest in the Novo-G FPGA computer from the NSF Center for High Performance Reconfigurable Computing (CHREC); this year’s HPCS has a track on HPRC, and several workshops with an HPRC focus have been organized in the last few years.
Intended Audience
The principal audience consists of three main groups. The first is the HPRC architectures research community: the book will provide a comprehensive overview of the state of the art in architectures, which will inform the researchers and engineers in this field. Researches will learn from the state of the art to develop better architectures; the book will show engineers in industry which architectures are ready for commercial deployment.
The second the HPRC tools research community: high-level programming of FPGAs is a young and very dynamic field, the book will provide an overview of the current approaches, how well they perform and their application domains. The third experts from the applications domains, which will want to read the book to see how they could accelerate their applications using FPGAs.
Overall, this book will be a starting point and reference for future and existing researchers in HPRC. It will also serve as a reference for postgraduate taught courses on high performance and reconfigurable computing.
Parts:
With this book, we aim to give a comprehensive overview of Architectures, Tools and Applications for High-Performance Reconfigurable Computing (HPRC).
I. Architectures
The Part on architectures will introduce the different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHREC's Novo-G and EPCC's Maxwell systems and Maxeler's MaxRack technology; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFL's CONFETTI system.
II. Tools
The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on HLL-to-gates tools (such as Impulse-C, AutoESL, Maxeler 's /MaxCompiler/, MORA-C++); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsoft’s Kiwi and Alchemy projects).
III. Applications
The part on Applications will present case from several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling
List of Accepted Chapters
Architectures
- Low Cost High Performance Reconfigurable Computing
Javier Castillo, Universidad Rey Juan Carlos, Spain - High-speed torus interconnect on FPGAs
Dirk Pleiter, University of Regensburg, Germany - MEMSCALE: Re-architecting memory resources for clusters
Holger Froening , University of Heidelberg, Germany - Proposal: Accelerate Communication, not Computation!
Mondrian Nuessle, Holger Froening, Sven Kapferer, Ulrich Bruening, University of Heidelberg, Germany - High Performance Cryptanalysis and Bioinformatics on the FPGA-based Computers RIVYERA and COPACOBANA
Tim Guneysu, Bochum University, Germany -
An FPGA-based supercomputer for statistical physics: the weird case of Janus
Jose Miguel Gil Narvion, Universidad de Zaragoza, Spain - Processor nodes and networking in an architecture for embedded HPC
Fritz Mayer-Lindenberg , Technical University of Hamburg-Harburg, Germany - The Convey Hybrid Core Architecture
Bernd Klauer , Helmut-Schmidt-Universitaet Hamburg , Germany - High performance computing based on a high speed dynamic reconfiguration
Minoru Watanabe, Shizuoka University, Japan - FPGA-based HPRC Systems for Scientific Applications
Tsuyoshi Hamada, Yuichiro Shibata, Nagasaki university, Japan
Tools
- Assessing Productivity of High-Level Design Methodologies for High-Performance Reconfigurable Computers
Esam El-Araby, Catholic University of America, Saumil G. Merchant, Tarek El-Ghazawi, George Washington University, USA - Acceleration of the Discrete Element Method: From RTL to C-Based Design
Benjamin Carrion Schafer, NEC Japan, Japan - Maximum Performance Computing with dataflow engines
Oliver Pell, Maxeler, UK - OpenCL: A suitable solution to simplify and unify FPGA developments
Jonathan Passerat-Palmbach, Clermont University, Blaise Pascal University, France - Reconfiguring Arithmetic for HPC
Florent de Dinechin, ENS Lyon, France
Applications
- High-Performance Hardware Acceleration of Asset Simulations
Christian de Schryver, University of Kaiserslautern, Germany - High-Performance Data Processing over N-ary Trees
Valery Sklyarov, Iouliia Skliarova, University of Aveiro, Portugal - FPGA-Accelerated Molecular Dynamics
Martin Herbordt, Boston University, USA - FPGA-Accelerated BLASTP
Martin Herbordt, Boston University, USA - High-Performance and Scalable System Architecture for Hippocampal Neural Firing Activity Prediction Based on FPGA
Will Li, City University of Hong Kong, China, Ray Cheung, UCLA, USA - High performance implementation of RTM seismic modeling on FPGAs: architecture, arithmetic and power issues
Manoel Eusebio de Lima, Victor Medeiros, Federal University of Pernambuco , Brazil - Accelerating the SPICE Circuit Simulator using an FPGA - A Case Study
Nachiket Kapre, Imperial College London, UK, Andre DeHon, University of Pennsylvania, USA - Towards Efficient Solvers for Stencil-Based Equation Systems on FGPAs
Fabian Nowak, Karlsruher Institut fuer Technologie, Germany - FPGA-based HPRC for Stencil Computations
Kentaro Sano, Tohoku University, Yasushi Inoguchi, JAIST, Japan - FPGA-based HPRC for Bioinformatics Applications
Hideharu Amano, Keio University, Yoshiki Yamaguchi, Tsukuba University, Japan
Important Deadlines
Proposal Submission: 15 December 2011
Proposal Review Results: 5 January 2012
Manuscript Submission: 28 March 2012
First Round of Review: 30 April 2012
Final Manuscript Due: 30 May 2012
Submissions
Please email your proposals to the book editors:
Wim Vanderbauwhede <wim.vanderbauwhede@glasgow.ac.uk>
Khaled Benkrid <k.benkrid@ed.ac.uk>
Chapter Manuscript Preparation Guidelines:
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The suggested length of the chapter is 8,000-12,000 words.
Templates for Formatting. There is a mandatory template for use with Microsoft Word or LaTex.
Art guidelines. Please read the Artwork Guidelines (PDF), which explains the requirements for submitting figures that are acceptable to Springer for publication. Please pay particular attention to the guidelines about color figures; it is standard practice for Springer to publish all print books in black and white, and we will not reproduce any images in color, unless you arrange for prior approval with your publishing editor on this book.
Permissions. Please read the CopyRight Permissions Guidelines (.doc) that describes what material you will need to secure permission for in order for us to re-print any previously published material in your book. This document also provides a template letter to use when querying publishers over re-using their published work. Very importantly, you will need to fill out the attached document’s last page, the figure log, in order to let us know the status of all the figures in the book. Meaning whether they are originals created by you, or if they’ve been re-used from other sources.
Contributor agreements. We require the lead author from each chapter to complete and sign an agreement providing consent to have their work published in the book.