Student Project Proposals
This page contains proposals for Hons/MSci/MSc projects. The MSc in Computer Systems Engineering (MSc-CSE) is a joint degree between Computing Science and Electronics & Electrical Engineering.
If you're interested in one of these proposals or the corresponding research topic, please contact me, I will be happy to provide more information. I also welcome applications of international MSc students who are prepared to undertake the project with distance supervision.
Hons (L4) Project Proposals
Faster search: comparing document scoring algorithms
The aim of this project is to compare two different approaches to search in terms of performance. The first approach uses an "inverted index", a list of all documents in which a query term occurs; the second approach, called document filtering, compares a bag-of-words representation of a document against a fixed profile. The performance of these algorithms is determined to a large extent by the hardware on which they are run, especially by the performance of the memory hierarchy. By developing and comparing optimised versions of both approaches, the project will demonstrate under which circumstances each of them is the best choice. This work is important because inverted-index scoring is the dominant approach today but document filtering has the potential for acceleration on GPUs and FPGAs.
Requires good knowledge of C++
Synthetic document collections for evaluation of search systems
For performance evaluation of information retrieval systems, large collections of documents are required. Often there are difficulties in obtaining such collections (intellectual property rights, format of the collections, ...). Also, a given collections has a fixed behaviour, so to test e.g. a fast search system, several collections are required. To address this problem, we resort to creation of "synthetic" collections, consisting of automatically generated documents. Last year, a very successful project developed a synthetic document generator which is able to generate "synthetic" collections which are statistically identical to the original collection on which they are based. The individual documents are however not representative for the original collection. The aim of this project is to extend the synthetic document generatorto generate documents that are much closer to real documents in terms of the correlation between the terms within a document: if one term occurs in a document, other terms are likely to occur in the same document. Using clustering techniques or natural language models, it is possible to closely approximate actual documents.
Requires good knowledge of C++
An OpenCL API for high-level FPGA programming
OpenCL is the emerging standard for parallel programming on GPUs and multicore systems. FPGAs are a third type of high-performance hardware with fine-grained parallelism. We have developed a high-level FPGA programming framework, MORA, which provides a C++ API to program the FPGA. The aim of this project is to create an OpenCL version of the MORA API, with a focus on the interface between the host machine and the device.
Requires good knowledged of C/C++; knowledge of OpenCL is an advantage
Dynamic memory allocation for GPUs
OpenCL is the emerging standard for parallel programming on GPUs and multicore systems. Currently, OpenCL does not have dynamic memory allocation (new() ins C++ or malloc() in C). Dynamic memory would allow garbage collection required by many, such as GPU-based Virtual Machines. The purpose of this project is to implement dynamic memory allocation inside an OpenCL buffer.
Memory based File System for GPUs
OpenCL is the emerging standard for parallel programming on GPUs and multicore systems. Currently, there is no notion of "files" or "directories" in OpenCL. The purpose of this project is to implement a memory-based file system inside an OpenCL buffer. This file system can be populated both from the host and the device, providing a very flexible interaction model between host and GPU.
Requires good knowledged of C/C++; knowledge of OpenCL is an advantage
MRes/MResSE/MSc-CS/MSc-SE/MSc-IT Project Proposals
Implementing an Embedded Operating System for a Manycore Virtual Machine
Description:
This project aims to add Embedded Operating System support a specialised Virtual Machine (GannetVM) for manycore systems, e.g. using the open source real-time OS RTEMS or the Xilinx Micro-Kernel API. The source code of the Virtual Machine (in C++) will be provided, as well as a task-based SystemC implementation which is partitioned very similar to the intended OS port. If succesful, the developped system will be deployed on a Network-on-Chip based manycore system consisting of Microblaze processors on a Xilinx Virtex-5 FPGA.
Prerequisites
Requires good C/C++ skills. Familiarity with embedded operating systems (e.g. RTEMS) is an advantage.
Mapping of computations on heterogeneous cores
Description:
Future computing platforms will very likely consist of a large number of heterogeneous cores. These cores will communicate over a Network-on-Chip, so in principle every core can communicate with all others, but in practice the physical distance of the cores is an important factor in the performance of the system. One of the challenges of this type of platforms is to work out the optimal mapping of parts of a computation over different cores.
For this project, we assume that the applications is built from predefined library components ("blocks"). The placement of a set of blocks given a set of constraints is a challenging problem, even more so because in practice every core will have to execute multiple different tasks, and a given block can be implemented on different fabrics with different trade-offs.
The aim of this project is to investigate this problem, possible using constraint programming techniques, possibly modelling it as a directed-graph layout problem, minimising the length of the longest arc (minimising communication delays) whilst respecting energy consumption, technological constraints, and other criteria.
Prerequisites
None.
Verification of Gannet: A service-based System-on-Chip architecture
Description:
This project involves the practical application of model checking with the SPIN model checker.
Gannet is a System-on-Chip (SoC) architecture developed at the University of Glasgow for heterogeneous multicore systems. It has been developed to make it easier to design complex reconfigurable SoCs by providing a high-level programmable infrastructure.
The Gannet platform connects a set of cores over a network. Each core interfaces with the system through a special circuit called the service manager. The service manager runs programs (written in the Gannet language) that determine the way in which the cores work together to perform a task. As a result, the Gannet SoC is a complex, concurrent system, in which components communicate via channels.
Although thorough testing suggests that the system behaves as expected in most cases, we can not say with certainty that it behaves as expected in all cases. To do this, some form of formal verification is required.
The purpose of this project is to a create model of the Gannet service manager using the Promela modelling language (see [1]), which can then be verified using the SPIN model checker. The project will involve proving that the models are free of deadlock, and creating temporal properties that can be used to check that the associated systems behave as expected, or, if not, to produce a counter-example.
The student will have to teach him/herself Promela and SPIN beforehand (using [1] for example), to complete this project on time. Interested students may also find [2] useful.
[1] The Spin Model checker: Primer and reference manual. Addison-Wesley 2003.
[2] Model checking: a tutorial overview. Merz. Lecture Notes in Computing Science 2067, pp. 3-38, 2001
Special Requirements:
This project would be especially suitable for an Electronic and Software Engineering student.
A steady-state solver for an economic growth model discrete-event simulator
Description:
Economic growth models are an important tool to model the impact of changes to e.g. interest rates or taxation on economic growth. The initial steady state conditions for an economy cannot be determined trivially. However, they completely determine the evolution of the economy. It is therefore important to have the capability to determine the initial steady state within the simulator rather than having to rely on external tools such as MATLAB.
The aim of this project is to implement a steady-state solver for an economic growth model discrete-event simulator. The discrete-event simulator is implemented in the SystemC system-level design language because of its efficient event scheduler.
The student should become familiar with economic growth models beforehand, e.g. using [1]
[1] Robert J. Barro and Xavier Sala-i-Martin, "Economic Growth", 2nd Edition; Cambridge, Mass.; The MIT Press, 2003
Special Requirements:
Knowledge of C++ is essential
Knowledge of SystemC is desirable
Development of a Stand-alone version of the Gannet Virtual Machine
Aim
This project aims to modify a specialised Virtual Machine (GannetVM) for embedded systems to run stand-alone on the embedded PowerPC in a Virtex-II Pro FPGA, e.g. using the Xilinx Micro-Kernel API or the open source real-time OS RTEMS. The GannetVM currently runs on Linux on the PPC. The project can either be performed using the IBM Processor Development Kit or using the actual FPGA system.
Prerequisites
Requires good C/C++ skills.
Exploring the GannetOS
Outline
Gannet is the name of a novel type of System-on-Chip architecture called the Service-based Architecture (SBA), as well as the name of the language used to describe tasks executed by the SBA. The Gannet Virtual Machine is a specialised VM for embedded systems.
Aim
The aim of this project is to explore the potential of the GannetVM as an embedded operating system. This will involve adding features for task control in the VM, e.g. pausing, killing and rescheduling tasks.
Prerequisites
Knowledge of either Ruby or C++ is essential as the current VM is written in Ruby and machine translated to C++.
A compiler for Gannet-C
Outline
Gannet is the name of a novel type of System-on-Chip architecture called the Service-based Architecture (SBA), as well as the name of the language used to describe tasks executed by the SBA. Conceptually, Gannet is an intermediate language, comparable to an assembly language for a von Neumann architecture or the "intermediate representation" languages for virtual machines such as the JVM, the .NET Common Language Runtime or Parrot.
Syntactically and semantically however, Gannet is a higher-order functional language. The language syntax is based on S-expressions and most of the keywords are borrowed from Scheme and Haskell.
Gannet-C is a proposed language with C-style syntax and Gannet semantics. The main purpose of Gannet-C is to lower the adoption threshold by giving programmers a familiar syntax, while still mainting all advantages of Gannet.
Aim
The aim of the project is to create a compiler which will compile Gannet-C programs into the Gannet language.
Prerequisites
Knowledge of Haskell is essential, good knowledge of C/C++ is an asset.
A compiler and runtime for MORA-C++
Outline
MORA is the name of a novel type of System-on-Chip architecture optimised for multimedia processing, developed by the Universities of Massachusetts (US) and Calabria (IT). The MORA architecture consists of a matrix of simple processing cores each with a small amount of local memory. The system operates in pipelined dataflow fashion, i.e. results from a computation are directly transfered to the next core (in-memory processing). A special interconnect network can be programmed to select the recipient of the results. In terms of classification, MORA is a MIMD machine but also a coarse-grained dataflow machine.
Aim
The aim of the project is to develop a compiler and runtime library for MORA. By adhering strictly to a specific API, it is possible to program MORA in C++. The goal is to create a compiler which will parse the C++ code and emit code in MORA assembly language. The MORA assembly language was developed at the Department and we have developed an assembler to create MORA machine code. The compiler will complete the MORA toolchain.
Prerequisites
Knowledge of C++ is essential. For compiling into MORA assembler, we suggest the use of LLVM (the Low-level Virtual Machine) as the toolchain.
MSc-CSE Project Proposals
HW/SW Integration: FPGA acceleration of string matching using the MORA soft processor array
Outline
Hardware acceleration of string matching is an important field of research as it allows for real-time search of query terms in a document. The MORA soft processor array is an FPGA adaptation of a novel type of System-on-Chip architecture optimised for multimedia processing, developed in collaboration with the University of Massachusetts Lowell (US). The MORA framework provides a high-level FPGA programming approach. Creating FPGA applications using MORA does not require knowledge of VHDL or Verilog nor of the details of the hardware.
Aim
The aim of the project is to implement a string matching application on the MORA soft processor and interface it with the host system to demonstrate FPGA-accelerated search. The host system is an SGI Altix supercomputer running Linux, with an RC-100 FPGA board connected via a high-bandwidth NUMAlink interface. Interfacing between the host and the FPGA is facilitated using the SGI RASC (Reconfigurable Application Specific Computing) library. The specific aims of the project is to develop the glue logic between the MORA processor and the RASC interface, and the C code using the RASClib API to communicate with the FPGA (both based on RASC templates provided).
Prerequisites
The project requires good knowledge of Verilog or VHDL and C.
SystemC: Cycle-accurate model of the MORA processor array
Outline
MORA is the name of a novel type of System-on-Chip architecture optimised for multimedia processing, developed in collaboration with the University of Massachusetts Lowell (US). The MORA architecture consists of a matrix of simple processing cores each with a small amount of local memory. The system operates in pipelined dataflow fashion, i.e. results from a computation are directly transfered to the next core (in-memory processing). A special interconnect network can be programmed to select the recipient of the results. In terms of classification, MORA is a MIMD machine but also a coarse-grained dataflow machine.
Aim
The aim of the project is to develop a cycle-accurate SystemC model of the processor array. The purpose of this model is to allow rapid prototyping and exploration of new features and designs. A complete VHDL implementation of the archicture is available for reference.
Prerequisites
Good knowledge of C++ is essential, knowledge of SystemC, VHDL or Verilog is desirable.
SystemC: Cycle-approximate model of Quarc NoC integrated with Gannet
Outline
The Quarc NoC is a novel high-performance Network on Chip. In the previous years, two very successful MSc projects resulted in a FPGA implementation (in Verilog) of the Quarc NoC which led to several publications. For charcterisation of NoC-based SoCs, system-level models are essential. SystemC is the IEEE-standard industry leading system level modeling tool an as such the obvious choice.
Aim
The aim of this project is to develop a detailed transaction-level SystemC model of the Quarc. In particular, the aim is to integrate the Quarc SystemC model with the existing SystemC model for the novel Gannet SoC platform.
Prerequisites
Requires good C++ coding skills. Knowledge of SystemC and an understanding of Verilog is desirable. A considerable SystemC codebase is already present for the student to draw upon.
Verilog/ASIC: Extension and Optimisation for ASIC synthesis of the Gannet Service Manager
Outline
The Gannet project investigates a novel architecture for systems-on-chip (SoC), the service-based architecture. The key block of the architecture is the service manager module which provides a service-based interface between its local service core and the other services in the system. Last year a very successful project resulted in implementation of the core design of the service manager.
Aim
The aim of the project is extend the service manager design and optimise it for ASIC synthesis. The current service manager design (targeting an FPGA) is provided in Verilog. The project includes interfacing the service manager with a third-party service core. The deliverables should include: speed obtained by simulation of the back-annotated synthesised design; power consumption; area utilisation.
Prerequisites
Good knowledge of Verilog. The project requires the use of synthesis tools (Synopsys, Synplify or Cadence), experience with these tools is an asset.