Research
Systems-on-Chip Research
My main research topic is novel architectures for Systems-on-Chip, with a focus on high-level programmability. This research was supported by an EPSRC Advanced Research Fellowship grant. Check out my research blog for the latest news.
Gannet: a service-based SoC architecture
This work is concerned with data flows between tasks in a service-based System-on-Chip architecture. The research is structured as a project called Gannet, the code is available under an Open Source license at GannetCode.org. Read more....
Networks-on-Chip
Networks-on-Chip are an integral part of the service-based SoC architecture. Therefore my PhD student Mahmoud Moadeli works on analytical performance modelling of NoCs, in particular focusing on the Spidergon topology and its relative merits comapred to mesh, ring and torus topologies. Currently, the focus of this work is on QoS and multicasting in NoCs. Another PhD student, Faiz-ul Hassan, works on system-level modeling of NoCs using SystemC.
Reconfigurable hardware
A number of EngD students work on various aspects of reconfigurable hardware:
- Graham Milligan's thesis on dynamically reconfigurable Finite State Machines;
- Waqar Nabi has developed a coarse-grain reconfigurable architecture for power-efficient implementation of multiple wireless communications protocols. He pursues similar lines of research in his current function at COMSATS Institute of Information Technology in Pakistan.
- Paul Mckechnie works with Xilinx on reducing design errors in reconfigurable systems, covering aspects such as type checking, formal verification and instrumentation;
- Haitham Fattah works with Codeplay on compiler technologies for C++ that exploit the inherent parallelism in FPGAs.
Student project proposals
A number of proposals for DCS MSc/MSCi, DCS level3/4 and ISLI MSc projects, al relating to my research interests.
High-level FPGA programming research
Accelerating Information Retrieval using FPGAs
The FPGA4IR project, a collaboration with Dr Leif Azzopardi of the DCS IR group, aims at developing high-performance FPGA-accelerated Information Retrieval solutions. FPGAs can speed up IR algorithms significantly by exploiting the inherent parallelism.
For this project, sponsored by Matrixware, we use the SGI RC100 FPGA board connected to an SGI Altix 4700 NUMA machine (80 Itanium cores, 320GB memory). For programming the FPGAs we us Mitrion-C, a high-level language developped by Mitrionics.
We have demonstrated order-of-magnitude speed-ups for IR algorithms implemented on the RC100 compared to the same algorithms running on the Itanium. However, the FPGAs consume only a fraction of the power of an Itanium processor (4W compared to 80W). Clearly, FPGA implementations of IR algoritms could make search a lot greener.
The results of this work have been presented at the Information Retrieval Facility Symposium (IRFS 2008) in Vienna, the SIGIR09 conference in Boston and the FPL09 conference in Prague.
Greener Search in the News
Matrixware Press Release 09/02/2009
Xilinx XCell Journal Article Feb 2010
An very informal talk about FPGAs for Greener Search
The MORA Soft Processor Array
The MORA project is a collaboration with Prof. Martin Margala at UMass Lowell, aiming to develop a coarse-grained reconfigurable architecture for multimedia applications. My contribution to the project is the programming model and a novel low-level language to program the architecture. Our collaboration has already lead to several publications (ERSA09, AHS09, FPL09).
One objective of this research is to create a soft core version of MORA optimised for FPGAs. We have developped a complete tool chain which converts programs written in the MORA assembly language into an FPGA bitstream. Our preliminary findings have been submitted to ReConFig09.
High-level FPGA Programming using Hume
The Hume language "is a strongly typed, mostly-functional language with an integrated tool set for developing, proving and assessing concurrent, safety-critical systems. Hume aims to extend the frontiers of language design for resource-limited systems, including real-time embedded and safety-critical systems, by introducing new levels of abstraction and provability." In a collaboration with Heriot-Watt University in the framework of the Islay project, we are exploring several routes for high-level FPGA Programming using Hume.
Previous Research
Previous research (at Strathclyde University)