I'm looking for PhD students interested in the following topics. There is no guaranteed funding for these positions. Opportunities for scholarships depend on your country of origin, see the guidance on scholarships.
- Compilers and runtime systems for heterogeneous architectures, in particular FPGAs
The topic of this research is the development of a compiler for high-level programming of FPGAs in particular. However, the compiler will target OpenCL (e.g. using the recent SPIR draft for integration with LLVM) so that the code can also run on multicore CPUs and GPUs. If you are keen to undertake cutting-edge compiler research, this is the topic for you!
- Acceleration of scientific code on multicore CPUs, GPUs and FPGAs
The topic of this research is the development and application of automated refactoring and source translation technologies to scientific codes, in particular climate/weather-related simulation code, with the aim of efficient acceleration of these codes on multicore CPUs, GPUs and FPGAs. If you are interested in source-to-source compilation (e.g. the ROSE compiler framework), refactoring and GPUs or FPGAs, and have expertise in compiler technology, FPGA programming or GPU programming, this topic provides an exciting research opportunity.
- Acceleration of Information Retrieval algorithms on GPUs and FPGAs ("Greener Search")
The topic of this research is on accelerating search and data filtering algorithms using FPGAs and GPUs. In particular FPGAs have great potential for greening the data centres as they offer a very high performance-per-Watt. A lot depends on the actual algorithms, as well as the system partitioning. If you have expertise in FPGA programming would like to take part in the development of the next generation of low-power search technology, this is a great opportunity.
I am currently supervising and co-supervising 3 PhD students:
The research topics are:
- Ashkan Tousimojarad: Thread placement and cache optimisation manycore architectures
- Sharifa Al Khanjari: Advanced Management Techniques for Many-core Communication Systems
- Nasibeh Nasiri: development of a novel soft processor array for high-level FPGA programming (co-supervision with Prof. Martin Margala at UMass Lowell)
More information on this PhD research can be found on my research page.
I supervise and have supervised MSc, MSci and Hons student projects:
- 2014-2015: Pierre Hallot (MSc): "Extending an OpenCL Kernel for a Large Eddy Simulator with Halo Exchanges for Distributed Computing"
- 2014-2015: Georgios Goulos (MSc): "Extending the Glasgow Parallel Reduction Machine (GPRM) with MPI for use in clusters"
- 2014-2015: Kristian Hentschel (MSci): "FPGA Port of a Large Scientific Model from Legacy Code: The Emanuel Convection Scheme", this work was published at EMiT 2015 and ParCo 2015
- 2014-2015: Gordon Reid (MSci): "Exploring the parallelisation of the Large Eddy Simulation using MPI and the Glasgow Model Coupling Framework", see our GMCF repo.
- 2014-2015: Ross Meikleham (CS/Maths Hons): "Design and compilation of a C-like front end language for the GPRM", see our GPRM repo.
- 2014-2015: Gavin Davidson (CS Hons): "A Parallel Implementation of the Self Organising Map using OpenCL"
- 2014-2015: Ben Turner (CS Hons): "Finding a Maximum Clique With OpenCL"
- 2013-2014: Gordon Reid (CS Hons): GPU-Accelerated Document Filtering
- 2013-2014: Kristian Hentschel (ESE Hons): Implementing Insense with OpenCL
- 2013-2014: Dan Tomosoiu (CS Hons): GPU Acceleration of a Hurricane Simulator using OpenCL
- 2012: Jacky Luk (MSc SLI): A SystemC model for simulating MORA-OpenCL applications
- 2012: Marcin Bujar (ESE Hons): An OpenCL API for high-level FPGA programming
- 2012: Alex Waite (CS Hons): A Memory-based File System for use with OpenCL
- 2012: Magnus Morton (MSci): Auto-parallelisation of Python
- 2012: Florian Hartwig (MSci): an EDSL for OpenCL programming in Haskell
- 2011: Anton Frolov (MSc CSE): Generation of synthetic document collections for performance testing of Information Retrieval applications
- 2010: Bruno Izern (MSc SLI): A store-and-forward version of the Quarc Network-on-Chip
- 2010: Radwan Kershif: Desing and Implementation of a Novel Discrete Event Simulation Framework
- 2009: Georgios Karyotis (MSc SLI): FPGA Prototyping of the Quarc Network-on-Chip
- 2009: Galih Kanigoro (MSc IT): Design and Implementation of RAM-based File System
- 2008: Partha Maji: FPGA Implementation of the Quarc Network-on-Chip Switch. The results of this work have been published at the Reconfigurable Architectures Workshop (IPDPS-RAW-09) and the International Conference on Advanced Information Networking and Applications (AINA-09).
- 2008: Xiaofeng Wang: A Socket Interface for the Gannet Virtual Machine (MScIT)
- 2008: Grzegorz Login: Characterisation of an FPGA-based Packet Processing System
- 2007: Chidambaram Thirunavukkarasu: FPGA Implementation of the Service Manager Module for the Gannet SoC. The results of this work have been published at the NASA/ESA Conference on Adaptive Hardware and Systems (AHS2008)
- 2007: Tushar Jobanputra: FPGA Implementation of Core Services for the Gannet SoC
- 2007: Kunjan Patel: A Reliable Network Layer for TinyOS. This results of this work have been accepted for publication at the Symposium on Embedded and Pervasive Systems (EPS-09) (). Kunjan is now doing a PhD with Chris Bleakley at University College Dublin.
- 2007: Douglas Wylie: Service-based System-on-Chip
- 2006: Theodoros Geladaris: Design and implementation of firmware for a source-routed IP-over-USB2 network
- 2005: Matheos Lampropoulos and David McCuish: Design and implementation of an FPGA-based router
- 2005: Fong Chin Hsiung: Design and implementation of a source-routed network infrastructure using SystemC
- 2005: Laythe Al-Janabi: Porting of a Reconfigurable FSM Hardware Platform to SystemC
- 2005 Philipp Mayerhofer: Shapeshifter: a parametrisable soft-FPGA (AdvMSc)
- 2004: Eza Fauzana Mohd Sharaani: FPGA implementation and performance measurement for different configurations of the LEON soft core
- 2004: Dilin Valiparanbil Divakar: Design and implementation of an FPGA-based router for "smart" packets