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Version 0.9.4	Last update: Thu Sep 18 12:10:37 BST 2003

Verilog Code Generator

This Perl-Verilog code generator is available from CPAN as Verilog::CodeGen.

The Verilog hardware description language

The Verilog Hardware Description Language (IEEE-1364) is a language intended to model hardware systems (in particular, but by no means exclusively, electronic integrated circuits).

The basic entity in a Verilog program (often call a netlist) is the module. A module can be compared to a subroutine or function, but a better analogy is to visualise every module as a small IC.

Communication with the module happens only via (input and output) pins. All pins of all modules are interconnected with wires (generally called nets). Modules can send and receive signals via the pins and wires. A simple module definition is shown below.

module and_nor (A,B,C,Z); 

input A,B,C; 

output Z; 

wire Z_and; 

and x_and_0 (Z_and,A,B); 

nor x_nor_0 (Z,Z_and,C);

endmodule //and_nor

To use a module, the module is instantiated, this means an instance of the module is used with a particular connectivity. This could be compared to a subroutine call, with the very important difference that the timing of the execution is not determined by the position in the code but is triggered by the status of the input pins.

module two_and_nors (A,B,C,Z);

input [1:0] A,B,C; 

output [1:0] Z; 

and_nor x_and_nor_0 (Z[0],A[0],B[0],C[1]);

and_nor x_and_nor_1 (Z[1],A[1],B[1],C[0]);

endmodule //two_and_nors

As can be seen from the above example, modules are hierarchical, a module can contain any number of submodules.
To simulate the design, a special kind of module is used, generally called a testbench. This modules has no pins. It generates the initial stimuli which are applied to an instance of the top level module of the design, and generates a graphical or textual output.

Object-oriented code generator

I use this tool to design an optical packet switch. The OPS design has a large number of parameters (number of ports, number of wavelengths, buffer depth, switching time, unit packet length, bitrate etc). Because it would be very cumbersome to adapt the netlist for every change of a parameter, a code generator is used. Every module is represented by an object. The main purpose of the object is to generate the Verilog code. Essentially, every object is a subroutine following a strict template. When the subroutine is called with the new() method, a reference to the object is returned.

Consider following example:

$delayline=new('S_delay_line',delay=>$delay);

$code.=$delayline->inst('x_dl_1',A=>'IN',Z=>'indel');

In Perl, scalar variables are prefixed with a $ sign; the -> notation indicates an object method call; the => notation indicates the assignment of a value to an object property.

The first line creates a new S_delay_line object, $delayline, with a value $delay for the delay property. This already shows the big advantage of the code generator: a single object can generate a Verilog module for a delayline with an arbitrary delay. Without the generator, it would be necessary to create a specific module for every desired delay line.

The second line is the instantiation. The variable $code holds a string which represents the Verilog code. The inst() method call generates the Verilog code for an instance of the $delayline object with the desired connectivity and name. The .= command appends the output to the string.

An essential feature of the code generator is that it allows to use objects within objects. This way the complete hierarchical Verilog module structure is reflected in the object structure. Apart from that, the objects have a number of convenience methods to run simulations, plot results, search the generated code for patterns etc.

GUI frontend

The distribution contains a GUI frontend to the code generator.This GUI communicates with XEmacs to edit the object templates and view the parsed results. It allows to inspect the generated code with v2html, a Verilog to HTML translator, and to run the testbenches in Icarus Verilog.

More information

Read the documentation for all details.